Design Space Exploration of Split-Path Data Driven Dynamic Full Adder

This paper presents the design, the analysis and the complete characterization of a novel split-path Data Driven Dynamic (sp-D3L) full adder cell in IBM’s 65 nm CMOS process. The split path D3L design style derived from standard D3L allows the design of high speed dynamic circuits without the power overhead of the clock tree while providing significantly higher performance than the D3L due to reduced capacitance at the pre-charge node. To demonstrate the performance benefits of the new split-path dynamic approach, we present comparison of the proposed adder with conventional static and dynamic adder cells. All the adder circuits were characterized for speed, power, area, noise margins, supply voltage scaling as well as fan-out capabilities. To evaluate the combined impact of load driven by the adder and load presented by the adder to the driving circuit, a combined fan-infan-out analysis with varying loads was also performed. Monte Carlo simulations were performed to evaluate the reliability of the adder design against random process, voltage and temperature variations. To compare with state of the art, we also performed a comparison of our proposed adder with several low power as well as high performance adders proposed recently in literature. Furthermore, to simulate the behavior of the adder in data path elements, we built ripple carry adders of varying lengths using the proposed adder. The new design was found to achieve from 16% to 27% performance advantages over its static and dynamic counterparts at nominal supply voltage. With supply voltage scaled from 1 V to 0.8 V, the adder shows 12%, 34% and 39% PDP advantage over domino, static and conventional D3L designs respectively. Fan-out analysis showed the adder to perform with 11% to 41% better PDP than the others at worst case FO32 loading.